The present invention relates to a semiconductor device, an appliance on which the semiconductor device is mounted, and a method of producing the semiconductor device.
The demand for minimizing the size or thickness of semiconductor devices, including semiconductor integrated circuit chips, has sharply increased, particularly in IC packaging. A chip scale package technique (CSP) is known for producing IC packages, namely semiconductor packaged IC chips for use as memories, which are reduced to a size almost equal to the size of an IC element. One such CSP technique is disclosed in Japanese Patent Laid-open Publication No. H8-125066.
FIG. 8 is a cross-sectional view of a conventional chip scale package, in which a semiconductor element 1 has pads 2 mounted on a center region of the lower side thereof. A connector lead frame 4 is located and bonded by an electrically insulating adhesive 3 to the lower side of the semiconductor element 1. The connector lead frame 4 is connected by wires 5 to the pads 2 of the semiconductor element 1. The connector lead frame 4 has projections formed by e.g. etching. The entire assembly is sealed with a resin material 6, except for the projections of the lead frame 4, which must be exposed. The exposed projections of the connector lead frame 4 are coated with doses of solder paste which serve as external electrodes 7. The chip scale package is now completed.
However, such a conventional semiconductor device has some disadvantages. For example, forming of the connector lead frame by etching is an intricate task which is difficult to implement by a common pressing technique such as stamping as would serve to bring costs down. Also, sealing with resin is difficult since a particular region has to be exposed. This leads to deficiencies in technical quality.